Using hierarchy, designers can divide large FPGA designs that include a high number of IP cores or system components into smaller sub-systems.
#Altera quartus ii web edition 9.1 download#
Customers can download the reference design from the Qsys page of Altera's Web site at Qsys enables designers to develop large, scalable systems with a hierarchical design flow feature. The reference design demonstrates how an Altera-provided PCIe IP core saves months of development time by eliminating the need to develop Transaction Layer Packet (TLP) encoding/decoding logic and by simplifying PCIe protocol interface complexity. The design uses an automatically pipelined, NoC-based interconnect to packetize data for easier and faster transport. The reference design achieves throughput of over 1,400MB/s between a memory-mapped PCIe Gen2 x4 Endpoint and an external DDR3 memory.
To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe ® to DDR3 reference design built using Qsys. Qsys uses a NoC-based interconnect to deliver higher performance systems compared to conventional bus and switch fabric architectures. Qsys improves system scalability for large FPGA designs and enables support for industry standard interfaces (Avalon and AMBA ® AXI™ from ARM ®, etc). The new Qsys tool features the industry’s first FPGA-optimized network-on-a-chip (NoC)-based interconnect delivering up to 2X higher interconnect performance compared to SOPC Builder.
Version 11.0 features the production release of Altera's next-generation system integration tool, Qsys.
#Altera quartus ii web edition 9.1 software#
San Jose, Calif., May 9, 2011-Altera Corporation (Nasdaq: ALTR) today announced the release of its Quartus ® II software version 11.0, the industry’s number one software in performance and productivity for CPLD, FPGA and HardCopy ® ASIC designs. Industry's First FPGA-Optimized Network-on-a-Chip (NoC) Interconnect Delivers up to 2X the Performance versus SOPC Builder
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